Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), flash memory, dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM).
Conventional DRAM cells are comprised of a switching transistor and an integrated storage capacitor tied to the storage node of the transistor. Charge storage is enhanced by providing appropriate storage capacity in the form of a stacked capacitor or a trench capacitor in parallel with the depletion capacitance of the floating storage node. DRAM cells are volatile and therefore lose data when the power is removed.
DRAMs use one or more arrays of memory cells arranged in rows and columns. Each of the rows of memory cells is activated by a corresponding row line that is selected from a row address. A pair of complementary digit lines are provided for each column of the array and a sense amplifier coupled to the digit lines for each column is enabled responsive to a respective column address. The sense amplifier senses a small voltage differential between the digit lines and amplifies such voltage differential.
Due to finite charge leakage across the depletion layer, the capacitor has to be recharged frequently to ensure data integrity. This is referred to in the art as refreshing and can be accomplished by periodically coupling the memory cells in the row to one of the digit lines after enabling the sense amplifiers. The sense amplifiers then restore the voltage level on the memory cell capacitor to a voltage level corresponding to the stored data bit. The permissible time between refresh cycles without losing data depends on various factors such as rate of charge dissipation in the memory capacitor.
As computers become smaller and their performance increases, the computer components should also go through a corresponding size reduction and performance increase. To accomplish this, the capacitors and transistors of DRAM cells can be reduced in size. This has the effect of increased speed and memory density with decreased power requirements.
However, a problem with decreased capacitor size is that sensing a conventional DRAM cell requires a minimum value of capacitance per cell. As the capacitor gets smaller, the capacitance is reduced. This has become a scalability challenge for DRAM.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a more scalable DRAM cell.